modelsim 직장에서 올바른 verilog와 alu 4 비트(translate from):alu 4 bit with verilog in modelsim and work correct




File list:
Alu-4bit
.......\work
.......\....\@a@l@u_4@bit
.......\....\............\verilog.asm
.......\....\............\_primary.dat
.......\....\............\_primary.vhd
.......\....\@a@n@d_bit
.......\....\..........\verilog.asm
.......\....\..........\_primary.dat
.......\....\..........\_primary.vhd
.......\....\@complement
.......\....\...........\verilog.asm
.......\....\...........\_primary.dat
.......\....\...........\_primary.vhd
.......\....\@complement_2
.......\....\.............\verilog.asm
.......\....\.............\_primary.dat
.......\....\.............\_primary.vhd
.......\....\@decrement
.......\....\..........\verilog.asm
.......\....\..........\_primary.dat
.......\....\..........\_primary.vhd
.......\....\@full@adder
.......\....\...........\verilog.asm
.......\....\...........\_primary.dat
.......\....\...........\_primary.vhd
.......\....\@half@adder
.......\....\...........\verilog.asm
.......\....\...........\_primary.dat
.......\....\...........\_primary.vhd
.......\....\@increment
.......\....\..........\verilog.asm
.......\....\..........\_primary.dat
.......\....\..........\_primary.vhd
.......\....\@multiplier
.......\....\...........\verilog.asm
.......\....\...........\_primary.dat
.......\....\...........\_primary.vhd
.......\....\@o@r_bit
.......\....\........\verilog.asm
.......\....\........\_primary.dat
.......\....\........\_primary.vhd
.......\....\@ripple_@adder
.......\....\..............\verilog.asm
.......\....\..............\_primary.dat
.......\....\..............\_primary.vhd
.......\....\@subtract
.......\....\.........\verilog.asm
.......\....\.........\_primary.dat
.......\....\.........\_primary.vhd
.......\....\@subtract_@b
.......\....\............\verilog.asm
.......\....\............\_primary.dat
.......\....\............\_primary.vhd
.......\....\@transfer
.......\....\.........\verilog.asm
.......\....\.........\_primary.dat
.......\....\.........\_primary.vhd
.......\....\@x@o@r_bit
.......\....\..........\verilog.asm
.......\....\..........\_primary.dat
.......\....\..........\_primary.vhd
.......\....\decoder
.......\....\.......\verilog.asm
.......\....\.......\_primary.dat
.......\....\.......\_primary.vhd
.......\....\test
.......\....\....\verilog.asm
.......\....\....\_primary.dat
.......\....\....\_primary.vhd
.......\....\_info
.......\Alu-4bit.cr.mti
.......\Alu-4bit.mpf
.......\alu-4bit.v
.......\transcript
.......\vsim.wlf