8051 Verilog, testbench 포함하는 소스 코드를 C 언어 소스 코드를 디버거 무결성 및 실현에 직접 사용될 수있습니다.




File list:
oc8051
.....\asm
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.....\...\hex
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.....\...\...\cast.hex
.....\...\...\counter_test.hex
.....\...\...\div16u.hex
.....\...\...\divmul.hex
.....\...\...\fib.hex
.....\...\...\gcd.hex
.....\...\...\int2bin.hex
.....\...\...\interrupt_test.hex
.....\...\...\lcall.hex
.....\...\...\negcnt.hex
.....\...\...\r_bank.hex
.....\...\...\serial_test.hex
.....\...\...\sort.hex
.....\...\...\sqroot.hex
.....\...\...\testall.hex
.....\...\...\timer_test.hex
.....\...\...\xram.hex
.....\...\...\xram_m.ihx
.....\...\in
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.....\...\..\...\Repository
.....\...\..\...\Root
.....\...\..\cast.in
.....\...\..\counter_test.in
.....\...\..\div16u.in
.....\...\..\divmul.in
.....\...\..\fib.in
.....\...\..\gcd.in
.....\...\..\int2bin.in
.....\...\..\interrupt_test.in
.....\...\..\lcall.in
.....\...\..\negcnt.in
.....\...\..\oc8051_xrom.in
.....\...\..\r_bank.in
.....\...\..\serial_test.in
.....\...\..\sort.in
.....\...\..\sqroot.in
.....\...\..\testall.in
.....\...\..\test_xram.in
.....\...\..\timer2_test.in
.....\...\..\timer_test.in
.....\...\..\xram.in
.....\...\..\xram_m.in
.....\...\..\xrom_test.in
.....\...\v
.....\...\.\CVS
.....\...\.\...\Entries
.....\...\.\...\Repository
.....\...\.\...\Root
.....\...\.\cast.v
.....\...\.\counter_test.v
.....\...\.\div16u.v
.....\...\.\divmul.v
.....\...\.\fib.v
.....\...\.\gcd.v
.....\...\.\int2bin.v
.....\...\.\interrupt_test.v
.....\...\.\lcall.v
.....\...\.\negcnt.v
.....\...\.\r_bank.v
.....\...\.\serial_test.v
.....\...\.\sort.v
.....\...\.\sqroot.v
.....\...\.\testall.v
.....\...\.\timer_test.v
.....\...\.\xram.v
.....\...\.\xram_m.v
.....\...\vec
.....\...\...\CVS
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.....\...\...\...\Root
.....\...\...\cast.vec
.....\...\...\counter_test.vec
.....\...\...\div16u.vec
.....\...\...\divmul.vec
.....\...\...\fib.vec
.....\...\...\gcd.vec
.....\...\...\int2bin.vec
.....\...\...\interrupt_test.vec
.....\...\...\lcall.vec
.....\...\...\negcnt.vec
.....\...\...\r_bank.vec
.....\...\...\serial_test.vec
.....\...\...\sort.vec
.....\...\...\sqroot.vec
.....\...\...\testall.vec
.....\...\...\test_xram.vec
.....\...\...\timer2_test.vec
.....\...\...\timer_test.vec
.....\...\...\xram_m.vec
.....\...\...\xrom_test.vec
.....\...\cast.c
.....\...\counter_test.asm
.....\...\DIV16U.asm
.....\...\divmul.c
.....\...\fib.c
.....\...\gcd.c
.....\...\int2bin.c
.....\...\interrupt_test.asm
.....\...\lcall.asm
.....\...\negcnt.c
.....\...\r_bank.asm
.....\...\serial_test.asm
.....\...\sort.c
.....\...\sqroot.c
.....\...\test.asm
.....\...\testall.asm
.....\...\testall.c
.....\...\timer2_test.asm
.....\...\timer_test.asm
.....\...\xram.c
.....\...\xram_m.c
.....\...\xrom_test.asm
.....\bench
.....\.....\CVS
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.....\.....\in
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.....\.....\..\...\Root
.....\.....\..\7seg.in
.....\.....\..\blinkP10.in
.....\.....\..\BLINKY.in
.....\.....\..\calculator.in
.....\.....\..\cast.in
.....\.....\..\cordic.in
.....\.....\..\counter_test.in
.....\.....\..\Crc.in
.....\.....\..\cubicroots.in
.....\.....\..\div16u.in
.....\.....\..\divmul.in
.....\.....\..\fib.in
.....\.....\..\gcd.in
.....\.....\..\int2bin.in
.....\.....\..\interrupt_test.in
.....\.....\..\interrupt_test2.in
.....\.....\..\lcall.in
.....\.....\..\mx_test.in
.....\.....\..\mx_test.in~
.....\.....\..\negcnt.in
.....\.....\..\normalize.in
.....\.....\..\oc8051_rom.in
.....\.....\..\oc8051_xrom.in
.....\.....\..\pca_test.in
.....\.....\..\pwm.in
.....\.....\..\r_bank.in
.....\.....\..\serial_test.in
.....\.....\..\Sieve.in
.....\.....\..\sort.in
.....\.....\..\sqroot.in
.....\.....\..\sqroot_1.in
.....\.....\..\src.in
.....\.....\..\testall.in
.....\.....\..\test_xram.in
.....\.....\..\timer0.in
.....\.....\..\timer2_test.in
.....\.....\..\timer_test.in
.....\.....\..\wdog1.in
.....\.....\..\wdog2.in
.....\.....\..\wdog3.in
.....\.....\..\xram.in
.....\.....\..\xram_m.in
.....\.....\..\xrom_test.in
.....\.....\vec
.....\.....\...\CVS
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.....\.....\verilog
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.....\.....\.......\oc8051_fpga_tb.v
.....\.....\.......\oc8051_serial.v
.....\.....\.......\oc8051_tb.v
.....\.....\.......\oc8051_timescale.v
.....\.....\.......\oc8051_uart_test.v
.....\.....\.......\oc8051_xram.v
.....\.....\.......\oc8051_xrom.v
.....\CVS
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.....\doc
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.....\...\...\oc8051_spec.pdf
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.....\...\...\oc8051_design.doc
.....\rtl
.....\...\CVS
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.....\...\verilog
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.....\...\.......\...\Root
.....\...\.......\oc8051_acc.v
.....\...\.......\oc8051_alu.v
.....\...\.......\oc8051_alu_src_sel.v
.....\...\.......\oc8051_alu_test.v
.....\...\.......\oc8051_b_register.v
.....\...\.......\oc8051_cache_ram.v
.....\...\.......\oc8051_comp.v
.....\...\.......\oc8051_cy_select.v
.....\...\.......\oc8051_decoder.v
.....\...\.......\oc8051_defines.v
.....\...\.......\oc8051_divide.v
.....\...\.......\oc8051_dptr.v
.....\...\.......\oc8051_icache.v
.....\...\.......\oc8051_indi_addr.v
.....\...\.......\oc8051_int.v
.....\...\.......\oc8051_memory_interface.v
.....\...\.......\oc8051_multiply.v
.....\...\.......\oc8051_ports.v
.....\...\.......\oc8051_psw.v
.....\...\.......\oc8051_ram_256x8_two_bist.v
.....\...\.......\oc8051_ram_64x32_dual_bist.v
.....\...\.......\oc8051_ram_top.v
.....\...\.......\oc8051_rom.v
.....\...\.......\oc8051_sfr.v
.....\...\.......\oc8051_sp.v
.....\...\.......\oc8051_tc.v
.....\...\.......\oc8051_tc2.v
.....\...\.......\oc8051_timescale.v
.....\...\.......\oc8051_top.v
.....\...\.......\oc8051_uart.v
.....\...\.......\oc8051_wb_iinterface.v
.....\...\.......\read.me
.....\sim
.....\...\CVS
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.....\...\rtl_sim
.....\...\.......\bin
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.....\...\.......\...\INCA_libs
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.....\...\.......\...\.........\worklib
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.....\...\.......\...\.........\.......\...\Root
.....\...\.......\...\.........\.......\inca.linux.138.pak
.....\...\.......\...\cds.lib
.....\...\.......\...\hdl.var
.....\...\.......\CVS
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.....\...\.......\...\Root
.....\...\.......\log
.....\...\.......\...\CVS
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.....\...\.......\...\...\Repository
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.....\...\.......\...\ncelab.log
.....\...\.......\...\ncsim.log
.....\...\.......\...\ncvlog.log
.....\...\.......\out
.....\...\.......\...\CVS
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.....\...\.......\...\waves.shm
.....\...\.......\...\.........\CVS
.....\...\.......\...\.........\...\Entries
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.....\...\.......\...\.........\...\Root
.....\...\.......\...\cast.out
.....\...\.......\...\counter_test.out
.....\...\.......\...\div16u.out
.....\...\.......\...\divmul.out
.....\...\.......\...\fib.out
.....\...\.......\...\gcd.out
.....\...\.......\...\int2bin.out
.....\...\.......\...\interrupt_test.out
.....\...\.......\...\lcall.out
.....\...\.......\...\ncelab.out
.....\...\.......\...\ncprep.out
.....\...\.......\...\ncvlog.out
.....\...\.......\...\negcnt.out
.....\...\.......\...\r_bank.out
.....\...\.......\...\serial_test.out
.....\...\.......\...\sort.out
.....\...\.......\...\sqroot.out
.....\...\.......\...\testall.out
.....\...\.......\...\timer.out
.....\...\.......\...\timer_test.out
.....\...\.......\...\xram_m.out
.....\...\.......\...\xrom_m.out
.....\...\.......\run
.....\...\.......\...\CVS
.....\...\.......\...\...\Entries
.....\...\.......\...\...\Repository
.....\...\.......\...\...\Root
.....\...\.......\...\internal.do
.....\...\.......\...\make
.....\...\.......\...\make_fpga
.....\...\.......\...\make_verilog
.....\...\.......\...\oc8051_defines.v
.....\...\.......\...\oc8051_timescale.v
.....\...\.......\...\run
.....\...\.......\...\run_sim.scr
.....\...\.......\...\verilog.log
.....\...\.......\src
.....\...\.......\...\CVS
.....\...\.......\...\...\Entries
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.....\...\.......\...\verilog
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.....\...\.......\oc8051_ea.in
.....\...\.......\oc8051_eai.in
.....\...\.......\oc8051_eax.in
.....\sw
.....\..\CVS
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.....\..\source
.....\..\......\CVS
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.....\..\......\...\Root
.....\..\......\p8051Rom.dof
.....\..\......\p8051Rom.dpr
.....\..\......\p8051Rom.res
.....\..\......\uMain.dcu
.....\..\......\uMain.dfm
.....\..\......\uMain.pas
.....\..\oc8051_Rom_Maker.exe
.....\..\read.me
.....\syn
.....\...\CVS
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.....\...\src
.....\...\...\CVS
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.....\...\...\verilog
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.....\...\...\.......\...\Repository
.....\...\...\.......\...\Root
.....\...\...\.......\disp.v
.....\...\...\.......\oc8051_cache_ram.v
.....\...\...\.......\oc8051_fpga_top.v
.....\...\...\.......\oc8051_ram.v
.....\...\...\.......\oc8051_rom.v
.....\...\...\.......\read.me
.....\...\synplify
.....\...\........\CVS
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.....\...\........\rev_1
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.....\...\........\rev_3
.....\...\........\.....\CVS
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.....\...\........\oc8051.prd
.....\...\........\oc8051.prj
.....\.nclaunch.dd