자일링스 EDK 빠른 학습 자료를 제작. 부드러운 - 코어 CPU, 전반적인 시스템의 유연성과 확장성을 개선하기 위해 자일링스 FPGA에 EDK 아키텍처.




File list:
EDK_for_Busy_People
..................\lab1
..................\....\code
..................\....\....\linker_script
..................\....\....\system.c
..................\....\....\timer_interrupt.c
..................\....\data
..................\....\....\system.ucf
..................\....\etc
..................\....\...\bitgen.opt
..................\....\...\bitgen.ut
..................\....\...\download.cmd
..................\....\...\fast_runtime.opt
..................\....\...\xc18v04_vq44.bsd
..................\....\sim.do
..................\....\system.mhs
..................\....\system.mhs.solution
..................\....\system.mss.solution
..................\....\system.xmp.solution
..................\lab2
..................\....\code
..................\....\....\hello.c
..................\....\....\linker_script
..................\....\....\timer_interrupt.c
..................\....\data
..................\....\....\system.ucf
..................\....\etc
..................\....\...\bitgen.opt
..................\....\...\bitgen.ut
..................\....\...\download.cmd
..................\....\...\fast_runtime.opt
..................\....\...\lab2_golden.cmd
..................\....\...\xc18v04_vq44.bsd
..................\....\lab2_golden
..................\....\...........\download.bit
..................\....\myip
..................\....\....\bram_block_v1_00_a
..................\....\....\..................\hdl
..................\....\....\..................\...\vhdl
..................\....\....\..................\...\....\bram1_elaborate.vhd
..................\....\....\..................\...\....\bram2_elaborate.vhd
..................\....\sim.do
..................\....\system.mhs
..................\....\system.mss
..................\....\system.mvs
..................\....\system.xmp
..................\lab3
..................\....\code
..................\....\....\linker_script
..................\....\....\system.c
..................\....\data
..................\....\....\system.ucf
..................\....\etc
..................\....\...\bitgen.opt
..................\....\...\bitgen.ut
..................\....\...\download.cmd
..................\....\...\fast_runtime.opt
..................\....\...\xc18v04_vq44.bsd
..................\....\myip
..................\....\....\bram_block_v1_00_a
..................\....\....\..................\hdl
..................\....\....\..................\...\vhdl
..................\....\....\..................\...\....\bram1_elaborate.vhd
..................\....\....\..................\...\....\bram2_elaborate.vhd
..................\....\sim.do
..................\....\system.make
..................\....\system.mhs
..................\....\system.mss
..................\....\system.mvs
..................\....\system.xmp
..................\....\xps.cmd
..................\lab4
..................\....\code
..................\....\....\hello.c
..................\....\....\linker_script
..................\....\....\mem_test.c
..................\....\....\mem_test.c~
..................\....\....\mem_test2.c
..................\....\....\web.c
..................\....\....\web.c~
..................\....\....\web.h
..................\....\data
..................\....\....\ppc405_i
..................\....\....\........\lib
..................\....\....\........\...\compiler.opt
..................\....\....\libgen.opt
..................\....\....\platgen.opt
..................\....\....\simgen.opt
..................\....\....\system.make
..................\....\....\system.mhs
..................\....\....\system.mss
..................\....\....\system.ucf
..................\....\....\system.ucf~
..................\....\....\xpsxflow.opt
..................\....\etc
..................\....\...\bitgen.opt
..................\....\...\bitgen.ut
..................\....\...\download.cmd
..................\....\...\fast_runtime.opt
..................\....\...\system.mss
..................\....\...\xc18v04_vq44.bsd
..................\....\...\xccace.bsd
..................\....\...\_impact.cmd
..................\....\...\_impact.log
..................\....\myip
..................\....\....\bram_block_v1_00_a
..................\....\....\..................\hdl
..................\....\....\..................\...\vhdl
..................\....\....\..................\...\....\bram1_elaborate.vhd
..................\....\....\dcm_ip
..................\....\....\......\data
..................\....\....\......\....\dcm_ip_v2_0_0.mpd
..................\....\....\......\....\dcm_ip_v2_0_0.mpd~
..................\....\....\......\....\dcm_ip_v2_0_0.pao
..................\....\....\......\hdl
..................\....\....\......\...\vhdl
..................\....\....\......\...\....\dcm_ip.vhd
..................\....\....\ddr_clock_module_ref_v1_00_a
..................\....\....\............................\data
..................\....\....\............................\....\ddr_clock_module_ref_v2_0_0.mpd
..................\....\....\............................\....\ddr_clock_module_ref_v2_0_0.pao
..................\....\....\............................\hdl
..................\....\....\............................\...\vhdl
..................\....\....\............................\...\....\ddr_clock_module_ref.vhd
..................\....\....\jtagppc_cntlr_v1_00_a
..................\....\....\.....................\data
..................\....\....\.....................\....\jtagppc_cntlr_v2_0_0.mpd
..................\....\....\.....................\....\jtagppc_cntlr_v2_0_0.pao
..................\....\....\.....................\hdl
..................\....\....\.....................\...\verilog
..................\....\....\.....................\...\.......\jtagppc_cntlr.v
..................\....\....\.....................\...\vhdl
..................\....\....\.....................\...\....\jtagppc_cntlr.vhd
..................\....\system.bmm
..................\....\system.log
..................\....\system.make
..................\....\system.mhs
..................\....\system.mss
..................\....\system.mvs
..................\....\system.xmp
..................\....\xps.cmd
..................\lab5
..................\....\code
..................\....\....\system.c
..................\....\data
..................\....\....\system_stub.ucf
..................\....\etc
..................\....\...\bitgen.opt
..................\....\...\bitgen.ut
..................\....\...\download.cmd
..................\....\...\fast_runtime.opt
..................\....\...\xc18v04_vq44.bsd
..................\....\...\_impact.cmd
..................\....\...\_impact.log
..................\....\myip
..................\....\....\bram_block_v1_00_a
..................\....\....\..................\hdl
..................\....\....\..................\...\vhdl
..................\....\....\..................\...\....\bram1_elaborate.vhd
..................\....\mymisc
..................\....\......\dcm_ip.vhd
..................\....\......\system_stub_edit.vhd
..................\....\readme.txt
..................\....\system.mhs
..................\....\system.mss
..................\....\system.mvs
..................\....\system.xmp
..................\....\xmd.ini
..................\....\xps.cmd
..................\EDK_overview.ppt
..................\EDK_Overview_lab1.doc
..................\EDK_Overview_lab2.doc
..................\EDK_Overview_lab3.doc
..................\EDK_Overview_lab4.doc
..................\EDK_Overview_lab5.doc
..................\integrate_my_ip_w_platgen.doc
..................\README_FIRST.htm