소스 인터페이스 vga 시험 절차, 언어 Verilog - vga




File list:
vga
..\xst
..\...\work
..\...\....\vlg04
..\...\....\.....\vga_wb_slave.bin
..\...\....\vlg05
..\...\....\.....\vga_wb_master.bin
..\...\....\vlg07
..\...\....\.....\vga_fifo_dc.bin
..\...\....\.....\vga_pgen.bin
..\...\....\vlg34
..\...\....\.....\generic_dpram.bin
..\...\....\vlg4D
..\...\....\.....\vga_csm_pb.bin
..\...\....\.....\vga_vtim.bin
..\...\....\vlg53
..\...\....\.....\generic_spram.bin
..\...\....\vlg59
..\...\....\.....\vga_clkgen.bin
..\...\....\vlg5D
..\...\....\.....\vga_fifo.bin
..\...\....\vlg5F
..\...\....\.....\vga_colproc.bin
..\...\....\vlg6A
..\...\....\.....\vga_enh_top.bin
..\...\....\vlg7B
..\...\....\.....\vga_tgen.bin
..\...\....\hdllib.ref
..\__projnav
..\.........\coregen.rsp
..\.........\runXst_tcl.rsp
..\.........\vga.gfl
..\.........\vga_enh_top.xst
..\.........\vga_flowplus.gfl
..\.........\xst_sprjTOstx_tcl.rsp
..\automake.log
..\coregen.log
..\coregen.prj
..\generic_dpram.v
..\generic_spram.v
..\prjname.lso
..\sync_check.v
..\tests.v
..\test_bench_top.v
..\timescale.v
..\vga.dhp
..\vga.npl
..\vga_clkgen.v
..\vga_colproc.v
..\vga_csm_pb.v
..\vga_curproc.v
..\vga_cur_cregs.v
..\vga_defines.v
..\vga_enh_top.cmd_log
..\vga_enh_top.lso
..\vga_enh_top.prj
..\vga_enh_top.stx
..\vga_enh_top.syr
..\vga_enh_top.v
..\vga_enh_top_vhdl.prj
..\vga_fifo.v
..\vga_fifo_dc.v
..\vga_pgen.v
..\vga_tgen.v
..\vga_vtim.v
..\vga_wb_master.v
..\vga_wb_slave.v
..\wb_b3_check.v
..\wb_mast_model.v
..\wb_model_defines.v
..\wb_slv_model.v
..\__projnav.log