RTL은 Verilog (자판기)의 완전한 소스 코드는 직접 검사로 사용할 수 있습니다.(translate from):RTL in Verilog (Vending Machine) complete source code can be directly used by the test.




File list:
vending_machine
..............\compile
..............\.......\contents.lib~vending_machine
..............\.......\sources.sth
..............\.......\vcp_cmd.log
..............\.......\vending_machine.epr
..............\.......\vending_machine.erf
..............\.......\vending_machine.opt
..............\.......\vending_machine.opv
..............\log
..............\...\console.log
..............\src
..............\...\integer2bcd.v
..............\...\vending_machine.v
..............\...\waveform.awf
..............\0vending_machine.mgf
..............\1vending_machine.mgf
..............\3vending_machine.mgf
..............\bde.set
..............\compilation.order
..............\compile.cfg
..............\Edfmap.ini
..............\elaboration.log
..............\projlib.cfg
..............\synthesis.order
..............\vending_machine.adf
..............\vending_machine.LIB
..............\vending_machine.rlb
..............\vending_machine.wsp
..............\vending_machine_0.rep
lab04.aws
lab04.wsw
library.cfg