이것은 VHDL 언어의 RAM에 대한 설명입니다, 그건 아, 고전적인 소스 코드의 무결성, 그리고이 직접적으로 사용될 수있습니다.




File list:
DEMO_45_RAM
..........\DB
..........\..\altsyncram_4qb1.tdf
..........\..\altsyncram_9gm2.tdf
..........\..\decode_ogi.tdf
..........\..\RAM_DP1.(0).cnf.cdb
..........\..\RAM_DP1.(0).cnf.hdb
..........\..\RAM_DP1.(1).cnf.cdb
..........\..\RAM_DP1.(1).cnf.hdb
..........\..\RAM_DP1.(10).cnf.cdb
..........\..\RAM_DP1.(10).cnf.hdb
..........\..\RAM_DP1.(11).cnf.cdb
..........\..\RAM_DP1.(11).cnf.hdb
..........\..\RAM_DP1.(12).cnf.cdb
..........\..\RAM_DP1.(12).cnf.hdb
..........\..\RAM_DP1.(13).cnf.cdb
..........\..\RAM_DP1.(13).cnf.hdb
..........\..\RAM_DP1.(14).cnf.cdb
..........\..\RAM_DP1.(14).cnf.hdb
..........\..\RAM_DP1.(15).cnf.cdb
..........\..\RAM_DP1.(15).cnf.hdb
..........\..\RAM_DP1.(2).cnf.cdb
..........\..\RAM_DP1.(2).cnf.hdb
..........\..\RAM_DP1.(3).cnf.cdb
..........\..\RAM_DP1.(3).cnf.hdb
..........\..\RAM_DP1.(4).cnf.cdb
..........\..\RAM_DP1.(4).cnf.hdb
..........\..\RAM_DP1.(5).cnf.cdb
..........\..\RAM_DP1.(5).cnf.hdb
..........\..\RAM_DP1.(6).cnf.cdb
..........\..\RAM_DP1.(6).cnf.hdb
..........\..\RAM_DP1.(7).cnf.cdb
..........\..\RAM_DP1.(7).cnf.hdb
..........\..\RAM_DP1.(8).cnf.cdb
..........\..\RAM_DP1.(8).cnf.hdb
..........\..\RAM_DP1.(9).cnf.cdb
..........\..\RAM_DP1.(9).cnf.hdb
..........\..\RAM_DP1.asm.qmsg
..........\..\RAM_DP1.cbx.xml
..........\..\RAM_DP1.cmp.cdb
..........\..\RAM_DP1.cmp.hdb
..........\..\RAM_DP1.cmp.kpt
..........\..\RAM_DP1.cmp.logdb
..........\..\RAM_DP1.cmp.rdb
..........\..\RAM_DP1.cmp.tdb
..........\..\RAM_DP1.cmp0.ddb
..........\..\RAM_DP1.dbp
..........\..\RAM_DP1.db_info
..........\..\RAM_DP1.eco.cdb
..........\..\RAM_DP1.fit.qmsg
..........\..\RAM_DP1.hier_info
..........\..\RAM_DP1.hif
..........\..\RAM_DP1.map.cdb
..........\..\RAM_DP1.map.hdb
..........\..\RAM_DP1.map.logdb
..........\..\RAM_DP1.map.qmsg
..........\..\RAM_DP1.pre_map.cdb
..........\..\RAM_DP1.pre_map.hdb
..........\..\RAM_DP1.psp
..........\..\RAM_DP1.rtlv.hdb
..........\..\RAM_DP1.rtlv_sg.cdb
..........\..\RAM_DP1.rtlv_sg_swap.cdb
..........\..\RAM_DP1.sgdiff.cdb
..........\..\RAM_DP1.sgdiff.hdb
..........\..\RAM_DP1.signalprobe.cdb
..........\..\RAM_DP1.sld_design_entry.sci
..........\..\RAM_DP1.sld_design_entry_dsc.sci
..........\..\RAM_DP1.syn_hier_info
..........\..\RAM_DP1.tan.qmsg
..........\5_RAM.MIF
..........\cmp_state.ini
..........\FITFSTIO.TXT
..........\RAM_DP.GDF
..........\RAM_DP1.ACF
..........\RAM_DP1.asm.rpt
..........\RAM_DP1.BDF
..........\RAM_DP1.CDF
..........\RAM_DP1.CNF
..........\RAM_DP1.done
..........\RAM_DP1.dpf
..........\RAM_DP1.FIT
..........\RAM_DP1.fit.rpt
..........\RAM_DP1.fit.smsg
..........\RAM_DP1.fit.summary
..........\RAM_DP1.flow.rpt
..........\RAM_DP1.HIF
..........\RAM_DP1.map.rpt
..........\RAM_DP1.map.summary
..........\RAM_DP1.MIF
..........\RAM_DP1.MMF
..........\RAM_DP1.NDB
..........\RAM_DP1.PIN
..........\RAM_DP1.pof
..........\RAM_DP1.QPF
..........\RAM_DP1.QSF
..........\RAM_DP1.QWS
..........\RAM_DP1.SNF
..........\RAM_DP1.SOF
..........\RAM_DP1.tan.rpt
..........\RAM_DP1.tan.summary
..........\RAM_DP1_assignment_defaults.qdf
..........\RAM_DQ0.BSF
..........\RAM_DQ0.VHD
..........\实验3_2.pdf