Verilog 구현 스톱워치 프로그램입니다. 이 절차를 수행하지만, 수정할 수있습니다 게재 시계 디자인. 디자인이 필요 매초마다 달성에 따르면하실 수있습니다. 동시에 변경할 수있습니다 주도 및 기타 절차를 실행합니다. 아주 강력한!




File list:
clock
....\db
....\..\clock.(0).cnf.cdb
....\..\clock.(0).cnf.hdb
....\..\clock.(1).cnf.cdb
....\..\clock.(1).cnf.hdb
....\..\clock.(2).cnf.cdb
....\..\clock.(2).cnf.hdb
....\..\clock.(3).cnf.cdb
....\..\clock.(3).cnf.hdb
....\..\clock.(4).cnf.cdb
....\..\clock.(4).cnf.hdb
....\..\clock.(5).cnf.cdb
....\..\clock.(5).cnf.hdb
....\..\clock.asm.qmsg
....\..\clock.cbx.xml
....\..\clock.cmp.bpm
....\..\clock.cmp.cdb
....\..\clock.cmp.ecobp
....\..\clock.cmp.hdb
....\..\clock.cmp.logdb
....\..\clock.cmp.rdb
....\..\clock.cmp.tdb
....\..\clock.cmp0.ddb
....\..\clock.cmp_bb.cdb
....\..\clock.cmp_bb.hdb
....\..\clock.cmp_bb.logdb
....\..\clock.cmp_bb.rcf
....\..\clock.dbp
....\..\clock.db_info
....\..\clock.eco.cdb
....\..\clock.eds_overflow
....\..\clock.fit.qmsg
....\..\clock.hier_info
....\..\clock.hif
....\..\clock.map.bpm
....\..\clock.map.cdb
....\..\clock.map.ecobp
....\..\clock.map.hdb
....\..\clock.map.logdb
....\..\clock.map.qmsg
....\..\clock.map_bb.cdb
....\..\clock.map_bb.hdb
....\..\clock.map_bb.logdb
....\..\clock.pre_map.cdb
....\..\clock.pre_map.hdb
....\..\clock.psp
....\..\clock.pss
....\..\clock.rtlv.hdb
....\..\clock.rtlv_sg.cdb
....\..\clock.rtlv_sg_swap.cdb
....\..\clock.sgdiff.cdb
....\..\clock.sgdiff.hdb
....\..\clock.signalprobe.cdb
....\..\clock.sim.cvwf
....\..\clock.sim.hdb
....\..\clock.sim.qmsg
....\..\clock.sim.rdb
....\..\clock.sld_design_entry.sci
....\..\clock.sld_design_entry_dsc.sci
....\..\clock.syn_hier_info
....\..\clock.tan.qmsg
....\..\clock.tis_db_list.ddb
....\..\prev_cmp_clock.asm.qmsg
....\..\prev_cmp_clock.fit.qmsg
....\..\prev_cmp_clock.map.qmsg
....\..\prev_cmp_clock.qmsg
....\..\prev_cmp_clock.tan.qmsg
....\..\wed.wsf
....\bcdcnt.bsf
....\bcdcnt.v
....\bcdcnt.v.bak
....\clock.asm.rpt
....\clock.bdf
....\clock.cdf
....\clock.done
....\clock.dpf
....\clock.fit.rpt
....\clock.fit.smsg
....\clock.fit.summary
....\clock.flow.rpt
....\clock.map.rpt
....\clock.map.smsg
....\clock.map.summary
....\clock.pin
....\clock.pof
....\clock.qpf
....\clock.qsf
....\clock.qws
....\clock.sim.rpt
....\clock.sof
....\clock.tan.rpt
....\clock.tan.summary
....\clock.vwf
....\fenpin.bsf
....\fenpin.v
....\fenpin.v.bak
....\fenpin16.bsf
....\fenpin16.v
....\fenpin16.v.bak
....\fenpin4.bsf
....\fenpin4.v
....\fenpin4.v.bak
....\p7seg.bsf
....\p7seg.v
....\p7seg.v.bak