UART 통신 디자인 VHDL에 기반: PC 시리얼 포트 (RS232) 통신 CPLD의 실현. CPLD 행 및 FIFO (선입 메모리의 경우)에서 처음에 쓴 데이터 PC 8 비트 데이터를 받을 수 있습니다, 그리고 다음 8 비트 데이터의 완료를 PC로 전송 후 FIFO 로부터 제거는 CPLD 수신. 테스트를 통과 했다.




File list:
UART_TVHDL
.........\db
.........\..\add_sub_5nh.tdf
.........\..\prev_cmp_UART_TVHDL.asm.qmsg
.........\..\prev_cmp_UART_TVHDL.fit.qmsg
.........\..\prev_cmp_UART_TVHDL.map.qmsg
.........\..\prev_cmp_UART_TVHDL.qmsg
.........\..\prev_cmp_UART_TVHDL.tan.qmsg
.........\..\UART_TVHDL.(0).cnf.cdb
.........\..\UART_TVHDL.(0).cnf.hdb
.........\..\UART_TVHDL.(1).cnf.cdb
.........\..\UART_TVHDL.(1).cnf.hdb
.........\..\UART_TVHDL.(10).cnf.cdb
.........\..\UART_TVHDL.(10).cnf.hdb
.........\..\UART_TVHDL.(11).cnf.cdb
.........\..\UART_TVHDL.(11).cnf.hdb
.........\..\UART_TVHDL.(12).cnf.cdb
.........\..\UART_TVHDL.(12).cnf.hdb
.........\..\UART_TVHDL.(13).cnf.cdb
.........\..\UART_TVHDL.(13).cnf.hdb
.........\..\UART_TVHDL.(2).cnf.cdb
.........\..\UART_TVHDL.(2).cnf.hdb
.........\..\UART_TVHDL.(3).cnf.cdb
.........\..\UART_TVHDL.(3).cnf.hdb
.........\..\UART_TVHDL.(4).cnf.cdb
.........\..\UART_TVHDL.(4).cnf.hdb
.........\..\UART_TVHDL.(5).cnf.cdb
.........\..\UART_TVHDL.(5).cnf.hdb
.........\..\UART_TVHDL.(6).cnf.cdb
.........\..\UART_TVHDL.(6).cnf.hdb
.........\..\UART_TVHDL.(7).cnf.cdb
.........\..\UART_TVHDL.(7).cnf.hdb
.........\..\UART_TVHDL.(8).cnf.cdb
.........\..\UART_TVHDL.(8).cnf.hdb
.........\..\UART_TVHDL.(9).cnf.cdb
.........\..\UART_TVHDL.(9).cnf.hdb
.........\..\UART_TVHDL.ae.hdb
.........\..\UART_TVHDL.asm.qmsg
.........\..\UART_TVHDL.cbx.xml
.........\..\UART_TVHDL.cmp.cdb
.........\..\UART_TVHDL.cmp.hdb
.........\..\UART_TVHDL.cmp.logdb
.........\..\UART_TVHDL.cmp.rdb
.........\..\UART_TVHDL.cmp.tdb
.........\..\UART_TVHDL.cmp0.ddb
.........\..\UART_TVHDL.db_info
.........\..\UART_TVHDL.eco.cdb
.........\..\UART_TVHDL.fit.qmsg
.........\..\UART_TVHDL.hier_info
.........\..\UART_TVHDL.hif
.........\..\UART_TVHDL.lpc.html
.........\..\UART_TVHDL.lpc.rdb
.........\..\UART_TVHDL.lpc.txt
.........\..\UART_TVHDL.map.cdb
.........\..\UART_TVHDL.map.hdb
.........\..\UART_TVHDL.map.logdb
.........\..\UART_TVHDL.map.qmsg
.........\..\UART_TVHDL.pre_map.cdb
.........\..\UART_TVHDL.pre_map.hdb
.........\..\UART_TVHDL.rpp.qmsg
.........\..\UART_TVHDL.rtlv.hdb
.........\..\UART_TVHDL.rtlv_sg.cdb
.........\..\UART_TVHDL.rtlv_sg_swap.cdb
.........\..\UART_TVHDL.sgate.rvd
.........\..\UART_TVHDL.sgate_sm.rvd
.........\..\UART_TVHDL.sgdiff.cdb
.........\..\UART_TVHDL.sgdiff.hdb
.........\..\UART_TVHDL.sld_design_entry.sci
.........\..\UART_TVHDL.sld_design_entry_dsc.sci
.........\..\UART_TVHDL.syn_hier_info
.........\..\UART_TVHDL.tan.qmsg
.........\..\UART_TVHDL.tis_db_list.ddb
.........\..\UART_TVHDL.tmw_info
.........\incremental_db
.........\..............\compiled_partitions
.........\..............\...................\UART_TVHDL.root_partition.map.kpt
.........\..............\README
.........\UART.vhd
.........\UART.vhd.bak
.........\UART_FIFO.vhd
.........\UART_TVHDL.asm.rpt
.........\UART_TVHDL.cdf
.........\UART_TVHDL.done
.........\UART_TVHDL.dpf
.........\UART_TVHDL.fit.rpt
.........\UART_TVHDL.fit.summary
.........\UART_TVHDL.flow.rpt
.........\UART_TVHDL.map.rpt
.........\UART_TVHDL.map.summary
.........\UART_TVHDL.pin
.........\UART_TVHDL.pof
.........\UART_TVHDL.qpf
.........\UART_TVHDL.qsf
.........\UART_TVHDL.qws
.........\UART_TVHDL.tan.rpt
.........\UART_TVHDL.tan.summary
.........\UART_TVHDL.vhd
.........\UART_TVHDL.vhd.bak
.........\基于VHDL的UART通讯设计.docx