FPGA에 VHDL 이더넷 구현(translate from):VHDL ethernet implementation on a FPGA




File list:
ipv4_packet_transmitter
......................\branches
......................\tags
......................\trunk
......................\.....\IPv4_PACKET_TRANSMITTER
......................\.....\.......................\ALLOW_ZERO_UDP_CHECKSUM.vhd
......................\.....\.......................\comp_11b_equal.ngc
......................\.....\.......................\comp_11b_equal.vhd
......................\.....\.......................\comp_11b_equal.xco
......................\.....\.......................\comp_6b_equal.ngc
......................\.....\.......................\comp_6b_equal.vhd
......................\.....\.......................\comp_6b_equal.xco
......................\.....\.......................\COUNTER_11B_EN.vhd
......................\.....\.......................\COUNTER_6B_LUT_FIFO_MODE.vhd
......................\.....\.......................\dist_mem_64x8.ngc
......................\.....\.......................\dist_mem_64x8.vhd
......................\.....\.......................\dist_mem_64x8.xco
......................\.....\.......................\ENABLE_USER_DATA_TRANSMISSION.vhd
......................\.....\.......................\IPV4_LUT_INDEXER.vhd
......................\.....\.......................\IPV4_PACKET_TRANSMITTER.vhd
......................\.....\.......................\OVERRIDE_LUT_CONTROL.vhd
......................\.....\.......................\REG_16B_WREN.vhd
......................\.....\.......................\TARGET_EOF.vhd
......................\.....\LUT COE file
......................\.....\............\definition2_ipv4_lut.coe
......................\.....\README.txt