VHDL 소스 코드와 개발의 DDR SDRAM 컨트롤러




File list:
doc
..\ddr_sdram.pdf
model
....\mt46v4m16.vhd
....\mti_pkg.vhd
route
....\ddr_sdram.csf
....\ddr_sdram.esf
....\ddr_sdram.psf
....\ddr_sdram.quartus
....\ddr_sdram.vqm
....\pll1.vhd
simulation
.........\work
.........\....\altcam
.........\....\......\behave.dat
.........\....\......\behave.psm
.........\....\......\_primary.dat
.........\....\altclklock
.........\....\..........\behavior.dat
.........\....\..........\behavior.psm
.........\....\..........\_primary.dat
.........\....\altlvds_rx
.........\....\..........\behavior.dat
.........\....\..........\behavior.psm
.........\....\..........\_primary.dat
.........\....\altlvds_tx
.........\....\..........\behavior.dat
.........\....\..........\behavior.psm
.........\....\..........\_primary.dat
.........\....\command
.........\....\.......\rtl.dat
.........\....\.......\rtl.psm
.........\....\.......\_primary.dat
.........\....\control_interface
.........\....\.................\rtl.dat
.........\....\.................\rtl.psm
.........\....\.................\_primary.dat
.........\....\ddr_command
.........\....\...........\rtl.dat
.........\....\...........\rtl.psm
.........\....\...........\_primary.dat
.........\....\ddr_control_interface
.........\....\.....................\rtl.dat
.........\....\.....................\rtl.psm
.........\....\.....................\_primary.dat
.........\....\ddr_data_path
.........\....\.............\rtl.dat
.........\....\.............\rtl.psm
.........\....\.............\_primary.dat
.........\....\ddr_sdram
.........\....\.........\rtl.dat
.........\....\.........\rtl.psm
.........\....\.........\_primary.dat
.........\....\ddr_sdram_tb
.........\....\............\rtl.dat
.........\....\............\rtl.psm
.........\....\............\_primary.dat
.........\....\io_utils
.........\....\........\body.dat
.........\....\........\body.psm
.........\....\........\_primary.dat
.........\....\........\_vhdl.psm
.........\....\lpm_components
.........\....\..............\body.dat
.........\....\..............\body.psm
.........\....\..............\_primary.dat
.........\....\..............\_vhdl.psm
.........\....\mt46v4m16
.........\....\.........\behave.dat
.........\....\.........\behave.psm
.........\....\.........\_primary.dat
.........\....\mti_pkg
.........\....\.......\body.dat
.........\....\.......\body.psm
.........\....\.......\_primary.dat
.........\....\.......\_vhdl.psm
.........\....\pll1
.........\....\....\syn.dat
.........\....\....\syn.psm
.........\....\....\_primary.dat
.........\....\std_logic_arith
.........\....\...............\body.dat
.........\....\...............\body.psm
.........\....\...............\_primary.dat
.........\....\...............\_vhdl.psm
.........\....\util_1164
.........\....\.........\body.dat
.........\....\.........\body.psm
.........\....\.........\_primary.dat
.........\....\.........\_vhdl.psm
.........\....\_info
.........\APEX20KE_MF.VHD
.........\ddr_command.vhd
.........\ddr_control_interface.vhd
.........\ddr_data_path.vhd
.........\ddr_sdram.vhd
.........\ddr_sdram_tb.vhd
.........\io_utils.vhd
.........\lpm_pack.vhd
.........\modelsim.ini
.........\mt46v4m16.vhd
.........\mti_pkg.bak
.........\mti_pkg.vhd
.........\pll1.vhd
.........\readme.txt
.........\stdlogar.vhd
.........\util1164.vhd
.........\wave.do
source
.....\ddr_command.vhd
.....\ddr_control_interface.vhd
.....\ddr_data_path.vhd
.....\ddr_sdram.vhd
synthesis
........\synplicity
........\..........\rev_1
........\..........\.....\ddr_sdram.srm
........\..........\.....\ddr_sdram.srr
........\..........\.....\ddr_sdram.srs
........\..........\.....\ddr_sdram.tcl
........\..........\.....\ddr_sdram.tlg
........\..........\.....\ddr_sdram.vqm
........\..........\.....\ddr_sdram.xrf
........\..........\.....\ddr_sdram_cons.tcl
........\..........\.....\ddr_sdram_rm.tcl
........\..........\ddr_sdram.prj
readme.txt